EDA & architecture IP · A Synopsys–Cadence duopoly
Nearly every chip is designed with Synopsys and Cadence EDA tools, which are hard to replace; in 2025 the US briefly restricted EDA exports to China, later rescinded.
20 segments · 54 companies
From design tools, equipment and wafer fabs to chips, packaging and end markets: compute, memory, analog & power and RF each run on their own cycle and customers.
Upstream on the left, end demand on the right. Figures are 1-month returns; the segment shows its median.
Median price return of the listed companies in each segment.
Concentrated, hard-to-replace links that can cap the whole chain.
Nearly every chip is designed with Synopsys and Cadence EDA tools, which are hard to replace; in 2025 the US briefly restricted EDA exports to China, later rescinded.
Chips at 7nm and below need EUV lithography, and only ASML makes it at volume; limited annual output and long lead times pace leading-edge capacity.
Leading-edge nodes and most AI chips are made at TSMC; rivals trail on yield and capacity, and new fabs take years and huge capital.
Only SK hynix, Samsung and Micron make HBM at volume; slow yield and capacity ramps make HBM supply a limit on AI chip shipments.
AI and cloud storage need high-capacity hard drives, made mainly by Seagate and Western Digital; capacity is booked beyond 2026 and lead times run near a year.
Hub links every company to its suppliers and customers, with news and alerts as the chain moves.